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add_multirange_attribute
function.node->multirange_dimensions
vector, and as it doesn't do anything related tonode->attributes
, the name could be considered misleading. I'm renaming it toset_multirange_dimensions
and will be happy to consider other options, too.packed_ranges
andunpacked_ranges
in a single call, so that it's easier to forbid multiple calls of the function later on.process_net
function has a bug which causes ranges to be duplicated. With the current solution, the same range is added to a node here: https://github.com/chipsalliance/yosys-f4pga-plugins/blob/main/systemverilog-plugin/UhdmAst.cc#L501 and here: https://github.com/chipsalliance/yosys-f4pga-plugins/blob/main/systemverilog-plugin/UhdmAst.cc#L542The solution is that during the part when
process_*
functions are executed, we should store information about the ranges in attributes, and later on in the simplification process replace the attributes with children nodes.Input:
Result without the changes:
Result with the changes and Surelog
654c4fe230
and7689edf1
:The size of the input/output wires is fixed.
With the current Surelog (
bf13c83
) it doesn't appear to break anything, and also fixes one FV test.CI with the changes:
https://github.com/antmicro/yosys-systemverilog/actions/runs/5309555386
https://github.com/antmicro/yosys-systemverilog/actions/runs/5290316276